Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Document Table of Contents Accessing the Voltage Sensor Using FPGA Core Access

During user mode, you can implement a soft IP to access the voltage sensor block. To access the voltage sensor block from the core fabric, you need to include the following WYSIWYG atom in your Intel® Quartus® Prime project:

WYSIWYG Atom to Access the Voltage Sensor Block

.clk (<input>, clock signal from core),
.reset(<input>, reset signal from core),
.corectl(<input>, core enable signal from core),
.coreconfig(<input>, config signal from core),
.confin(<input>, config data signal from core),
.chsel(<input>, 4 bits channel selection signal from core),
.eoc(<output>, end of conversion signal from vsblock),
.eos(<output>, end of sequence signal from vsblock),
.dataout(<output>, 12 bits data out of vsblock)
Table 95.  Description for the Voltage Sensor Block WYSIWYG
Port Name Type Description
clk Input Clock signal from the core. The voltage sensor supports up to 11-MHz clock.
reset Input Active high reset signal. The reset signal has to asynchronously transition from high-to-low for the voltage sensor to start conversion. All registers are cleared and the internal voltage sensor clock is gated off when the reset signal is high.
corectl Input Active high signal. "1" indicates the voltage sensor is enabled for core access. "0" indicates the voltage sensor is disabled for core access.
coreconfig Input Serial configuration signal. Active high.
confin Input Serial input data from the core to configure the configuration register. The configuration register for the core access mode is 8-bit wide. LSB is the first bit shifted in.
chsel[3:0] Input 4-bit channel address. Specifying the channel to be converted.
eoc Output Indicates the end of the conversion. This signal is asserted after the conversion of each channel data.
eos Output Indicates the end of sequence. This signal is asserted after the completion of the conversion in one cycle of the selected sequence.
dataout[11:0] Output
  • dataout[11:6]—6-bit output data.
  • dataout[5:0]—Reserved.

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