1.1.4. LAB Control Signals
The LAB control block generates up to three clocks using the two clock sources and three clock enable signals. An inverted clock source is considered as an individual clock source. Each clock and the clock enable signals are linked.
Deasserting the clock enable signal turns off the corresponding LAB-wide clock.
The LAB row clocks [5..0] and LAB local interconnects generate the LAB-wide control signals. The inherent low skew of the MultiTrack interconnect allows clock and control signal distribution in addition to data. The MultiTrack interconnect consists of continuous, performance-optimized routing lines of different lengths and speeds used for inter- and intra-design block connectivity.
Clear and Preset Logic Control
LAB-wide signals control the logic for the register’s clear signal. The ALM directly supports an asynchronous clear function. The register preset is implemented as the NOT-gate push-back logic in the Quartus® Prime Pro Edition software. Each LAB supports up to two clears.
Intel® Cyclone® 10 GX devices provide a device-wide reset pin (DEV_CLRn) that resets all the registers in the device. You can enable the DEV_CLRn pin in the Quartus® Prime Pro Edition software before compilation. The device-wide reset signal overrides all other control signals.
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