10.4.2.1.2. Accessing the Voltage Sensor in the Core Access Mode when MD[1:0] is not Equal to 2'b11
The following timing diagram shows the requirement of the IP core to access the voltage sensor in the core access mode when MD[1:0] is not equal to 2'b11.
- Low-to-high transition for the corectl signal enables the core access mode.
- Wait for a minimum of two clock pulses before proceeding to step 2.
- De-asserting the reset signal releases the voltage sensor from the reset state.
- Wait for a minimum two clock pulses before proceeding to step 3.
- Configure the voltage sensor by writing into the configuration registers and asserting the coreconfig signal for eight clock cycles. The configuration register for the core access mode is 8-bit wide and configuration data is shifted in serially into the configuration register.
- The coreconfig signal going low indicates the start of the conversion based on the configuration defined in the configuration register.
- Poll the eoc and eos status signals to check if conversion for the first channel defined by MD[1:0] is completed. Latch the output data on the dataout[5:0] signal at the falling edge of the eoc signal.
- Poll the eoc and eos status signals to check if conversion for the subsequent channels defined by MD[1:0] are completed. Latch the output data on the dataout[5:0] signal at the falling edge of the eoc signal.
- Repeat step 6 until the eos signal is asserted, indicating the completion of the conversion of one cycle on the channels specified by MD[1:0].
- Both the eoc and eos signals are asserted on the same clock cycle when the voltage sensor completes the conversion for the last channel.
- To interrupt the operation of the voltage sensor by writing into the configuration register can only be done after one cycle of the eos signal is over.
- When is sequence is completed, and if the corectl and reset signals remain unchanged, the conversion will repeat the same sequence again until corectl is 0 and reset is 1. If you want to measure other sequence, repeat step 2 to step 7.
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