Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

6.5.1. Intel® Cyclone® 10 GX Package Support for DDR3/DDR3L x40 with ECC or LPDDR3 x32 without ECC

You require two I/O banks to support:
  • One DDR3/DDR3L x40 (32 bits data + 8 bits ECC), or
  • One LPDDR3 x32 interface without ECC
Table 64.  Number of DDR3/DDR3L x40 Interfaces (with ECC) or LPDDR3 x32 Interfaces (without ECC) Supported Per Device Package
Note: For some device packages, you can also use the 3 V I/O banks for external memory interfaces. However, the maximum memory interface clock frequency is capped at 450 MHz. To use higher memory clock frequencies, exclude the 3 V I/O bank from external memory interfaces. The maximum frequency varies according to protocol rate, device speed grade, and usage of the Ping Pong PHY.
Product Line Package
U484 F672 F780
10CX085 1 1
10CX105 1 1 2
10CX150 1 1 2
10CX220 1 1 2

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