Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

6.8. External Memory Interfaces in Intel® Cyclone® 10 GX Devices Revision History

Document Version Changes
2019.01.07 Updated number of DDR3/DDR3L ×72 Interfaces (with ECC) single and dual-rank supported for package F672 of the 10CX085 device.
2018.06.14
  • Updated the number of supported DDR3/DDR3L x72 interfaces for device 10CX085, package F672 in Number of DDR3/DDR3L ×72 Interfaces (with ECC) Single and Dual-rank Supported Per Device Package table.
  • Removed LPDDR3 support x72 interfaces.
2017.06.21 Updated the note about the memory interfaces support to clarify that I/O banks with less than 48 pins can be used for data pins only. Therefore, all external memory interfaces require at least one 48-pins I/O bank to place the A/C pins.
2017.05.08 Initial release.

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