Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Document Table of Contents Controlling EPCQ-L Devices

During configuration, Intel® Cyclone® 10 GX devices enable the EPCQ-L device by driving its nCSO output pin low, which connects to the chip select (nCS) pin of the EPCQ-L device. Intel® Cyclone® 10 GX devices use the DCLK and ASDO pins to send operation commands and read address signals to the EPCQ-L device. The EPCQ-L device provides data on its serial data output (DATA[]) pin, which connects to the AS_DATA[] input of the Intel® Cyclone® 10 GX devices.

Note: If you wish to gain control of the EPCQ-L pins, hold the nCONFIG pin low and pull the nCE pin high. This causes the device to reset and tri-state the AS configuration pins.

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