Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

10.4.2.1.1. Configuration Registers for the Core Access Mode

The core access configuration register is an 8-bit register.

Figure 175. Core Access Configuration Register


Table 96.  Description for the Core Access Configuration Register
Bit Number Bit Name Description
D0 MD0

Mode select for channel sequencer:

  • MD[1:0]=2'b00—channel sequencer cycles from channel 2 to channel 7
  • MD[1:0]=2'b01—channel sequencer cycles from channel 0 to channel 7
  • MD[1:0]=2'b10—channel sequencer cycles from channel 0 to channel 1
  • MD[1:0]=2'b11—controlled by IP core. Specify the channel to be converted on chsel[3:0].
D1 MD1
D2 BU0

Channel 0—Register bit that indicate channel 0. Set to "0" for unipolar selection.

D3 BU1

Channel 1—Register bit that indicate channel 1. Set to "0" for unipolar selection.

D4 NA

Reserved. Set to "0".

D5 NA

Reserved. Set to "0".

D6 CAL

Calibration enable bit. "0" indicates calibration is off, "1" indicates calibration is on. The calibration result is not included in the final 12-bit converted data when calibration is off.

D7 NA

Reserved. Set to "0".

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