Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

8.3. CRAM Error Detection Settings Reference

To define these settings in the Quartus® Prime Pro Edition software, point to Assignments > Device > Device and Pin Options > Error Detection CRC.
Figure 163.  Device and Pin Options Error Detection CRC Tab


Table 87.  CRC Errors Settings
Setting Description
Enable Error Detection CRC_ERROR pin Enables CRAM frame scanning
Enable open drain on CRC_ERROR pin Enables the CRC_ERROR pin as an open-drain output
Divide error check frequency by To guarantee the availability of a clock, the EDCRC function operates on an independent clock generated internally on the FPGA itself. To enable EDCRC operation on a divided version of the clock, select a value from the list.

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