Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

4.1.3.3. Periphery Clock Networks

PCLK networks provide the lowest insertion delay and the same skew as RCLK networks.

Small Periphery Clock Networks

Each HSSI or I/O bank has 12 SPCLKs. SPCLKs cover one SCLK spine region in HSSI bank and one SCLK spine region in I/O bank adjacent to each other in the same row.

Figure 53. SPCLK Networks for Intel® Cyclone® 10 GX Devices This figure represents the top view of the silicon die that corresponds to a reverse view of the device package.


Large Periphery Clock Networks

Each HSSI or I/O bank has 2 LPCLKs. LPCLKs have larger network coverage compared to SPCLKs. LPCLKs cover one SCLK spine region in HSSI bank and one SCLK spine region in I/O bank adjacent to each other in the same row.

Did you find the information on this page useful?

Characters remaining:

Feedback Message