5.1. I/O and Differential I/O Buffers in Intel® Cyclone® 10 GX Devices
The general purpose I/Os (GPIOs) consist of LVDS I/O and 3 V I/O banks:
- LVDS I/O bank—supports differential and single-ended I/O standards up to 1.8 V. The LVDS I/O pins form pairs of true differential LVDS channels. Each pair supports a parallel input/output termination between the two pins. You can use each LVDS channel as transmitter only or receiver only. Each LVDS channel supports transmit SERDES and receive SERDES with DPA circuitry. For example, you use 10 channels of the available 24 channels as transmitters. Of the remaining channels, you can use 13 channels as receivers and one channel for the reference clock.
- 3 V I/O bank—supports single-ended and differential SSTL, HSTL, and HSUL I/O standards up to 3 V. Single-ended I/O within this I/O bank support all programmable I/O element (IOE) features except:
- Programmable pre-emphasis
- RD on-chip termination (OCT)
- Calibrated RS and RT OCT
- Internal VREF generation
Intel® Cyclone® 10 GX devices support LVDS on all LVDS I/O banks:
- All LVDS I/O banks support true LVDS input with RD OCT and true LVDS output buffer.
- The devices do not support emulated LVDS channels.
- The devices support both single-ended and differential I/O reference clock for the I/O PLL that drives the SERDES.
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