10.7.1. Power-Up Sequence Requirements for Intel® Cyclone® 10 GX Devices
The power rails in Intel® Cyclone® 10 GX devices are each divided into three groups. Refer to the Intel® Cyclone® 10 GX Device Family Pin Connection Guidelines and the AN 692: Power Sequencing Considerations for Intel® Cyclone® 10 GX, Intel® Arria® 10, and Intel® Stratix® 10 Devices for additional details.
The diagram below illustrates the voltage groups of the Intel® Cyclone® 10 GX devices and their required power-up sequence.
|Power Group||Intel® Cyclone® 10 GX Power Supplies|
All power rails in Group 1 must ramp up (in any order) to a minimum of 90% of their respective nominal voltage before the power rails from Group 2 can start ramping up.
The power rails within Group 2 can ramp up in any order after the last power rail in Group 1 ramps to the minimum threshold of 90% of its nominal voltage. All power rails in Group 2 must ramp to a minimum threshold of 90% of their nominal value before the Group 3 power rails can start ramping up.
The power rails within Group 3 can ramp up in any order after the last power rail in Group 2 ramps up to a minimum threshold of 90% of their full value.
For Intel® Cyclone® 10 GX devices, you can combine and ramp up Group 3 power rails with Group 2 power rails if the two groups share the same voltage level and the same voltage regulator as Group 2 power rail VCCPT.
All power rails must ramp up monotonically. The power-up sequence should meet either the standard or the fast Power On Reset (POR) delay time. The POR delay time depends on the POR delay setting you use. For the POR specifications of the Intel® Cyclone® 10 GX devices, refer to the POR Specifications section in the Intel® Cyclone® 10 GX Device Datasheet.
The power-up sequence must meet either the standard or fast POR delay time depending on the POR delay setting you use.
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