Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Document Table of Contents

7.1. Enhanced Configuration and Configuration via Protocol

Table 69.  Configuration Schemes and Features of Intel® Cyclone® 10 GX Devices Intel® Cyclone® 10 GX devices support 1.8 V programming voltage and several configuration schemes.
Scheme Data Width

Max Clock Rate


Max Data Rate


Decompression Design Security15 Remote System Update
JTAG 1 bit 33 33
Active Serial (AS) through the EPCQ-L configuration device

1 bit,

4 bits

100 400 Yes Yes Yes
Passive serial (PS) through CPLD or external microcontroller 1 bit 125 100 Yes Yes Parallel Flash Loader (PFL) IP core
Fast passive parallel (FPP) through CPLD or external microcontroller 8 bits 100 3200 Yes Yes PFL IP core
16 bits Yes Yes
32 bits Yes Yes
Configuration via Protocol [CvP (PCIe*)]

x1, x2, x4 lanes

5000 16 Yes Yes

You can configure Intel® Cyclone® 10 GX devices through PCIe using Configuration via Protocol (CvP). The Intel® Cyclone® 10 GX CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement.

14 Enabling either compression or design security features affects the maximum data rate. Refer to the Intel® Cyclone® 10 GX Device Datasheet for more information.
15 Encryption and compression cannot be used simultaneously.
16 Maximum rate is limited by the PCIe protocol overhead.

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