Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

2.5.1. Clocking Modes for Each Memory Mode

Table 10.  Memory Blocks Clocking Modes Supported for Each Memory Mode
Clocking Mode Memory Mode
Single-Port Simple Dual-Port True Dual-Port ROM
Single clock mode Yes Yes Yes Yes
Read/write clock mode Yes
Input/output clock mode Yes Yes Yes Yes
Independent clock mode Yes Yes
Note: The clock enable signals are not supported for write address, byte enable, and data input registers on MLAB blocks.

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