Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

2.10. Memory Blocks Asynchronous Clear

The M20K memory blocks support asynchronous clear on output latches and output registers. If your RAM does not use output registers, clear the RAM outputs using the output latch asynchronous clear.

The clear is an asynchronous signal pulse that you assert to clear the outputs. The internal logic extends the clear pulse until the next rising edge of the output clock. The outputs are cleared until you deassert the clear signal.

Figure 22. Output Latch Clear in Intel® Cyclone® 10 GX Devices (Non-ECC Mode)
Figure 23. Output Latch Clear in Intel® Cyclone® 10 GX Devices (ECC Mode)


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