The reset signal port of the IP core for each PLL is as follows:
- I/O PLL—reset
The reset signal is the reset or resynchronization input for each PLL. The device input pins or internal logic can drive these input signals.
When the reset signal is driven high, the PLL counters reset, clearing the PLL output and placing the PLL out-of-lock. The VCO is then set back to its nominal setting. When the reset signal is driven low again, the PLL resynchronizes to its input clock source as it re-locks.
You must assert the reset signal every time the PLL loses lock to guarantee the correct phase relationship between the PLL input and output clocks. You can set up the PLL to automatically reset (self-reset) after a loss-of-lock condition using the Quartus® Prime Pro Edition parameter editor.
You must include the reset signal if either of the following conditions is true:
- PLL reconfiguration or clock switchover is enabled in the design
- Phase relationships between the PLL input and output clocks must be maintained after a loss-of-lock condition
- If the input clock to the PLL is not toggling or is unstable when the FPGA transitions into user mode, reset the PLL after the input clock is stable and within specifications, even when the self-reset feature is enabled.
- If the PLL is not able to lock to the reference clock after reconfiguring the PLL or the external clock source, reset the PLL after the input clock is stable and within specifications, even when the self-reset feature is enabled.
- For fPLL, after device power-up, you must reset the fPLL when the fPLL power-up calibration process has completed (pll_cal_busy signal deasserts).
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