184.108.40.206. Dedicated Clock Input Pins
The sources of dedicated clock input pins are as follows:
- fPLL— REFCLK_GXB[L][C,D]_CH[B,T][p,n] from HSSI column
- I/O PLL— CLK_[2A, 2J, 2K, 2L, 3A, 3B]_[0,1][p,n] from I/O column
You can use the dedicated clock input pins for high fan-out control signals, such as asynchronous clears, presets, and clock enables, for protocol signals through the GCLK or RCLK networks.
The dedicated clock input pins can be either differential clocks or single-ended clocks for I/O PLL. For single-ended clock inputs, both the CLKp and CLKn pins have dedicated connections to the I/O PLL. fPLLs only support differential clock inputs.
Driving a PLL over a global or regional clock can lead to higher jitter at the PLL input, and the PLL will not be able to fully compensate for the global or regional clock. Intel recommends using the dedicated clock input pins for optimal performance to drive the PLLs.
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