Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

5.8. I/O and High Speed I/O in Intel® Cyclone® 10 GX Devices Revision History

Document Version Changes
2022.10.31
  • Added LVDS, RSDS, mini-LVDS, Differential POD12, and LVPECL to the list of I/O standards that support programmable I/O delay.
2022.09.29
  • Updated the outclk2 and outclk4 phase shift values in the topic listing the IOPLL parameter values for external PLL mode.
  • Added .qsf assignment information for on-chip differential I/O termination.
2022.08.03 Replaced the Guideline: Do Not Drive I/O Pins During Power Sequencing topic with the Guideline: Maximum Current Driving I/O Pins While Turned Off and During Power Sequencing topic.
2021.08.13 Updated the table that lists the SERDES transmitter I/O standards support to remove all previously listed I/O standards except True LVDS, mini-LVDS, and RSDS.
2019.12.27
  • Updated the programmable pre-emphasis diagram to remove the word "peak-peak".
  • Updated the pin placement guidelines for differential channels to clarify that the I/O bank PLL can drive transmitter channels in an adjacent I/O bank only in a wide transmitter interface that spans multiple I/O banks.
2019.05.07 Added a topic that provides a usage modes summary of the Intel® Cyclone® 10 GX LVDS SERDES.
2019.01.07
  • Updated I/O resource count for package F672 of the 10CX085 device.
  • Removed the MultiVolt I/O Interface in Intel® Cyclone® 10 GX Devices topic.
  • Updated the I/O Standards Voltage Levels in Intel® Cyclone® 10 GX Devices topic to add information about interfacing with systems of different voltages.
  • Removed statement that says that the programmable VOD value of "0" is not available for the LVDS I/O standard.
  • Removed ext_loaden signal in figures showing the LVDS receiver in soft-CDR mode.
  • Specified that connecting the IOPLL loaden signal to the LVDS receiver ext_loaden signal is not required for LVDS receivers in soft-CDR mode.
2018.02.02
  • In the topic about programmable open-drain output, changed the statement "logic-to-pin" to "logic to the output buffer".
  • Updated the number of pins in I/O banks 2J and 3A of package F672 of the 10CX085 device.
  • Removed the RSKM calculation example.
  • Updated the figure titles in the topic about LVPECL termination to clarify that the figures refer to external termination. There is no OCT support for LVPECL I/O standard.
  • Updated the guideline topic about pin placement for differential channels to clarify the following information:
    • In I/O banks used for differential receiver, the PLL can drive only the channels within the same I/O bank.
    • Unused pins within an I/O bank with the DPA feature enabled can be assigned to single ended I/O standards.
  • Clarified in the topic about I/O buffer and register that to utilize the I/O registers when implementing DDR circuitry, use the GPIO IP core.
  • Clarified that all singled-ended I/O assigned to the 3 V I/O bank supports all programmable I/O elements except programmable pre-emphasis, RD OCT, calibrated RS and RT OCT, and internal VREF generation.
  • Clarified that the 3 V I/O bank supports single-ended and differential SSTL, HSTL, and HSUL I/O standards.
  • Updated the topic about I/O and differential I/O buffers to specify that differential reference clock is supported for the I/O PLL that drives the SERDES.
  • Updated the guideline topic about VREF sources and VREF pins to specify that the VREF pins are dedicated for voltage-referenced signal-ended I/O standards.
Date Version Changes
November 2017 2017.11.10
  • Updated the note about driving LVDS channels with the PLL in integer PLL mode to clarify that you do not need a PLL if you bypass the SERDES.
  • Updated the topic about the serializer bypass for DDR and SDR operation to add more information about clocks to the IOE.
  • Updated the topic about the deserializer to add more information about bypassing the deserializer.
  • Removed the statement about SDR and DDR data width from the figures that show the receiver datapath in non-DPA, DPA, and soft-CDR modes.
  • Corrected typographical error in the example showing the parameter values to generate output clock in external PLL mode by updating "c0" to "outclk0".
  • Removed the note about the migration paths in the I/O Vertical Migration for Intel® Cyclone® 10 GX Devices.
  • Updated Differential SSTL-18 Class I and Class II, Differential SSTL-15 Class I and Class II, Differential SSTL-12 Class I and Class II , Differential 1.8 V HSTL Class I and Class II, Differential 1.5 V HSTL Class I and Class II, and Differential 1.2 V HSTL Class I and Class II I/O standards in Programmable Current Strength Settings for Intel® Cyclone® 10 GX table.
  • Added SSTL-12, SSTL-125, SSTL135, Differential SSTL-12, Differential SSTL-125, and Differential SSTL-135 I/O standards into Supported I/O Standards in FPGA I/O for Intel® Cyclone® 10 GX Devices and Intel® Cyclone® 10 GX I/O Standards Voltage Levels tables.
  • Removed DDR3 OCT Setting from Programmable Current Strength Settings for Intel® Cyclone® 10 GX Devices table and added a note to refer to On-Chip I/O Termination in Intel® Cyclone® 10 GX Devices section for I/O standards with DDR3 OCT Setting.
  • Updated programmable current strength values for SSTL-18 Class II and SSTL-15 Class II I/O standard in Programmable Current Strength Settings for Intel® Cyclone® 10 GX table.
  • Removed the note about 0.15mm package height difference between devices in the same package type in the I/O Vertical Migration for Intel® Cyclone® 10 GX Devices.
  • Removed the note about LVDS I/O bank assignment when using external memory devices more than 450MHz frequency in the I/O Vertical Migration for Intel® Cyclone® 10 GX Devices.
  • Removed RSKM Report for LVDS Receiver and Assigning Input Delay to LVDS Receiver Using TimeQuest Timing Analyzer chapters.
  • Added Guidelines: LVDS Reference Clock Source chapter.
  • Removed the statement about selecting the rising edge option in the parameter editor for the RX Non-DPA mode.
  • Removed LVDS Interface with the IOPLL IP Core for Transmitter Channels Spanning Multiple Banks Shared with Receiver Channels (DPA) Using Shared I/O PLL and LVDS Interface with the IOPLL IP Core for Transmitter Channels Spanning Multiple Banks Shared with Receiver Channels (With Soft-CDR Mode) Using Shared I/O PLL diagrams in Connection between IOPLL and LVDS SERDES in External PLL Mode chapter.
  • Updated Non-DPA LVDS Receiver Interface with IOPLL IP Core in External PLL Mode, DPA LVDS Receiver Interface with the IOPLL IP Core in External PLL Mode, Soft-CDR LVDS Receiver Interface with the IOPLL IP Core in External PLL Mode, and LVDS Transmitter Interface with the IOPLL IP Core in External PLL Mode diagrams in Connection between IOPLL and LVDS SERDES in External PLL Mode.
  • Rewrote the PLLs Driving DPA-Enabled Differential Receiver and Transmitter Channels in LVDS Interface Spanning Multiple I/O Banks guideline topic .
May 2017 2017.05.08 Initial release.

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