Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Document Table of Contents GCLK Control Block

You can select the clock source for the GCLK select block either statically or dynamically using internal logic to drive the multiplexer-select inputs.

When selecting the clock source dynamically, you can select either PLL outputs (such as C0 or C1), or a combination of clock pins or PLL outputs.

Figure 54. GCLK Control Block for Intel® Cyclone® 10 GX Devices

You can set the input clock sources and the clkena signals for the GCLK network multiplexers through the Quartus® Prime Pro Edition software using the ALTCLKCTRL IP core.

When selecting the clock source dynamically using the ALTCLKCTRL IP core, choose the inputs using the CLKSELECT[0..1] signal.

Note: You can only switch dedicated clock inputs from the same I/O or HSSI bank.

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