Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

4.1.5.4. PCLK Control Block

PCLK control block drives both SPCLK and LPCLK networks.

To drive the HSSI PCLK, select the HSSI output, fPLL output, or clock input pin.

To drive the I/O PCLK, select the DPA clock output, I/O PLL output, or clock input pin.

Figure 56. PCLK Control Block for HSSI Column for Intel® Cyclone® 10 GX Devices


Figure 57. PCLK Control Block for I/O Column for Intel® Cyclone® 10 GX Devices


You can set the input clock sources and the clkena signals for the PCLK networks through the Quartus® Prime Pro Edition software using the ALTCLKCTRL IP core.

Did you find the information on this page useful?

Characters remaining:

Feedback Message