Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Document Table of Contents Locked

The locked signal port of the IP core for each PLL is as follows:

  • fPLL—pll_locked
  • I/O PLL—locked

The lock detection circuit provides a signal to the core logic. The signal indicates when the feedback clock has locked onto the reference clock both in phase and frequency.

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