Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

6.4. External Memory Interface I/O Pins in Intel® Cyclone® 10 GX Devices

The memory interface circuitry is available in every I/O bank. The Intel® Cyclone® 10 GX devices feature differential input buffers for differential read-data strobe and clock operations.

The controller and sequencer in an I/O bank can drive address command (A/C) pins only to fixed I/O lanes location in the same I/O bank. The minimum requirement for the A/C pins are three lanes. However, the controller and sequencer of an I/O bank can drive data groups to I/O lanes in adjacent I/O banks (above and below).

Pins that are not used for memory interfacing functions are available as general purpose I/O (GPIO) pins.

Figure 113.  I/O Banks Interface SharingThis figure shows an example of two x16 interfaces shared by three I/O banks.


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