Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Document Table of Contents Column-Based and Frame-Based Check-Bits

Figure 155. Column-Based and Frame-Based Check-Bits

EDCRC Check-Bits Updates

Frame-based check-bits are calculated on-chip during configuration. Column-based check-bits are updated after configuration.

When you enable the EDCRC feature, after the device enters user mode, the EDCRC function starts reading CRAM frames. The data collected from the read-back frame is validated against the frame-based check-bits.

After the initial frame-based verification is completed, the column-based check-bits will be calculated based on the respective column CRAM. The EDCRC hard block will recalculate the column-based check-bits in one of the following scenarios:

  • FPGA re-configuration
  • After configuration via protocol (CvP) session

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