Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Document Table of Contents

2.7. Byte Enable in Embedded Memory Blocks

The embedded memory blocks support byte enable controls:

  • The byte enable controls mask the input data so that only specific bytes of data are written. The unwritten bytes retain the values written previously.
  • The write enable (wren) signal, together with the byte enable (byteena) signal, control the write operations on the RAM blocks. By default, the byteena signal is high (enabled) and only the wren signal controls the writing.
  • The byte enable registers do not have a clear port.
  • If you are using parity bits, on the M20K blocks, the byte enable function controls 8 data bits and 2 parity bits; on the MLABs, the byte enable function controls all 10 bits in the widest mode.
  • The LSB of the byteena signal corresponds to the LSB of the data bus.
  • The byte enable signals are active high.

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