Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

5.6.6.7.3. Connection between IOPLL and LVDS SERDES in External PLL Mode

Figure 105. Non-DPA LVDS Receiver Interface with IOPLL IP Core in External PLL Mode


Figure 106. DPA LVDS Receiver Interface with the IOPLL IP Core in External PLL ModeInvert the locked output port and connect it to the pll_areset port.


Figure 107. Soft-CDR LVDS Receiver Interface with the IOPLL IP Core in External PLL ModeInvert the locked output port and connect it to the pll_areset port.


Figure 108. LVDS Transmitter Interface with the IOPLL IP Core in External PLL ModeConnect the I/O PLL lvds_clk[1] and loaden[1] ports to the ext_fclk and ext_loaden ports of the LVDS transmitter.

The ext_coreclock port is automatically enabled in the LVDS IP core in external PLL mode. The Intel® Quartus® Prime compiler outputs error messages if this port is not connected as shown in the preceding figures.

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