Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

3.4. Block Architecture

The Intel® Cyclone® 10 GX variable precision DSP block consists of the following elements:

Table 24.  Block Architecture
DSP Implementation Fixed-Point Arithmetic Floating-Point Arithmetic
Block architecture
  • Input register bank
  • Pipeline register
  • Pre-adder
  • Internal coefficient
  • Multipliers
  • Adder
  • Accumulator and chainout adder
  • Systolic registers
  • Double accumulation register
  • Output register bank
  • Input register bank
  • Pipeline register
  • Multipliers
  • Adder
  • Accumulator and chainout adder
  • Output register bank

If the variable precision DSP block is not configured in fixed-point arithmetic systolic FIR mode, both systolic registers are bypassed.

Figure 25. Variable Precision DSP Block Architecture in 18 x 19 Mode for Fixed-Point Arithmetic in Intel® Cyclone® 10 GX Devices


Figure 26. Variable Precision DSP Block Architecture in 27 x 27 Mode for Fixed-Point Arithmetic in Intel® Cyclone® 10 GX Devices


Figure 27. Variable Precision DSP Block Architecture for Floating-Point Arithmetic in Intel® Cyclone® 10 GX Devices

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