- Accepts memory access commands from the core logic at half or quarter rate.
- Uses the Avalon-MM or Avalon-ST protocol. The default protocol is Avalon-ST. You can enable a hard adapter through a configuration register to make the input interface Avalon-MM compatible.
- The hard memory controller has a native Avalon-ST interface. You can instantiate a standard soft adaptor to bridge the Avalon-ST interface to AMBA AXI.
- To support all bypass modes and keep the port count minimum, the super set of all port lists is used as the physical width. Ports are shared among the bypass modes.
|Command generator and burst adapter
- Drains your commands from the input interface and feeds them to the timing bank pool.
- If read-modify-write is required, inserts the necessary read-modify-write read and write commands into the stream.
- The burst adapter chops your arbitrary burst length to the number specified by the memory types.
|Timing Bank Pool
- Key component in the memory controller.
- Sets parallel queues to track command dependencies.
- Signals the ready status of each command being tracked to the arbiter for the final dispatch.
- Big scoreboard structure. The number of entries is currently sized to 8 where it monitors up to 8 commands at the same time.
- Handles the memory access hazards (RAW, WAR and WAW) while part of the timing constraints are being tracked.
- High responsibility to assist the arbiter in implementing reordering:
- Row command reordering (activate and pre-charge).
- Column command reordering (read and write).
- When the pool is full, a flow control signal is sent back upstream to stall the traffic.
- Enforces the arbitration rules.
- Performs the final arbitration to select a command from all ready commands, and issues the selected command to the memory.
- Supports quasi-1T mode for half rate and quasi-2T mode for quarter rate.
- For the quasi modes, a row command must be paired with a column command.
Tracks the global timing constraints including:
- tFAW—the Four Activates Window parameter that specifies the time period in which only four activate commands are allowed.
- tRRD—the delay between back-to-back activate commands to different banks.
- Some of the bus turnaround time parameters.
- The host of all the configuration registers.
- Uses Avalon-MM bus to talk to the core.
- Core logic can read and write all the configuration bits.
- The debug bus is routed to the core through this block.
Executes the refresh and power down features.
Although ECC encoding and decoding is performed in soft logic13, the ECC controller maintains the read-modify-write state machine in the hard solution.
The memory controller communicates to the PHY using this interface.