Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook
ID
683775
Date
5/16/2025
Public
1. Logic Array Blocks and Adaptive Logic Modules in Cyclone® 10 GX Devices
2. Embedded Memory Blocks in Cyclone® 10 GX Devices
3. Variable Precision DSP Blocks in Cyclone® 10 GX Devices
4. Clock Networks and PLLs in Cyclone® 10 GX Devices
5. I/O and High Speed I/O in Cyclone® 10 GX Devices
6. External Memory Interfaces in Cyclone® 10 GX Devices
7. Configuration, Design Security, and Remote System Upgrades in Cyclone® 10 GX Devices
8. SEU Mitigation for Cyclone® 10 GX Devices
9. JTAG Boundary-Scan Testing in Cyclone® 10 GX Devices
10. Power Management in Cyclone® 10 GX Devices
2.1. Types of Embedded Memory
2.2. Embedded Memory Design Guidelines for Cyclone® 10 GX Devices
2.3. Embedded Memory Features
2.4. Embedded Memory Modes
2.5. Embedded Memory Clocking Modes
2.6. Parity Bit in Embedded Memory Blocks
2.7. Byte Enable in Embedded Memory Blocks
2.8. Memory Blocks Packed Mode Support
2.9. Memory Blocks Address Clock Enable Support
2.10. Memory Blocks Asynchronous Clear
2.11. Memory Blocks Error Correction Code Support
2.12. Embedded Memory Blocks in Cyclone® 10 GX Devices Revision History
3.4.1. Input Register Bank
3.4.2. Pipeline Register
3.4.3. Pre-Adder for Fixed-Point Arithmetic
3.4.4. Internal Coefficient for Fixed-Point Arithmetic
3.4.5. Multipliers
3.4.6. Adder
3.4.7. Accumulator and Chainout Adder for Fixed-Point Arithmetic
3.4.8. Systolic Registers for Fixed-Point Arithmetic
3.4.9. Double Accumulation Register for Fixed-Point Arithmetic
3.4.10. Output Register Bank
4.2.1. PLL Usage
4.2.2. PLL Architecture
4.2.3. PLL Control Signals
4.2.4. Clock Feedback Modes
4.2.5. Clock Multiplication and Division
4.2.6. Programmable Phase Shift
4.2.7. Programmable Duty Cycle
4.2.8. PLL Cascading
4.2.9. Reference Clock Sources
4.2.10. Clock Switchover
4.2.11. PLL Reconfiguration and Dynamic Phase Shift
5.1. I/O and Differential I/O Buffers in Cyclone® 10 GX Devices
5.2. I/O Standards and Voltage Levels in Cyclone® 10 GX Devices
5.3. Altera FPGA I/O IP Cores for Cyclone® 10 GX Devices
5.4. I/O Resources in Cyclone® 10 GX Devices
5.5. Architecture and General Features of I/Os in Cyclone® 10 GX Devices
5.6. High Speed Source-Synchronous SERDES and DPA in Cyclone® 10 GX Devices
5.7. Using the I/Os and High Speed I/Os in Cyclone® 10 GX Devices
5.8. I/O and High Speed I/O in Cyclone® 10 GX Devices Revision History
5.6.1. Cyclone® 10 GX LVDS SERDES Usage Modes
5.6.2. SERDES Circuitry
5.6.3. SERDES I/O Standards Support in Cyclone® 10 GX Devices
5.6.4. Differential Transmitter in Cyclone® 10 GX Devices
5.6.5. Differential Receiver in Cyclone® 10 GX Devices
5.6.6. PLLs and Clocking for Cyclone® 10 GX Devices
5.6.7. Timing and Optimization for Cyclone® 10 GX Devices
5.6.6.1. Clocking Differential Transmitters
5.6.6.2. Clocking Differential Receivers
5.6.6.3. Guideline: LVDS Reference Clock Source
5.6.6.4. Guideline: Use PLLs in Integer PLL Mode for LVDS
5.6.6.5. Guideline: Use High-Speed Clock from PLL to Clock LVDS SERDES Only
5.6.6.6. Guideline: Pin Placement for Differential Channels
5.6.6.7. LVDS Interface with External PLL Mode
5.7.1. I/O and High-Speed I/O General Guidelines for Cyclone® 10 GX Devices
5.7.2. Mixing Voltage-Referenced and Non-Voltage-Referenced I/O Standards
5.7.3. Guideline: Maximum Current Driving I/O Pins While Turned Off and During Power Sequencing
5.7.4. Guideline: Maximum DC Current Restrictions
5.7.5. Guideline: LVDS SERDES IP Core Instantiation
5.7.6. Guideline: LVDS SERDES Pin Pairs for Soft-CDR Mode
5.7.7. Guideline: Minimizing High Jitter Impact on Cyclone® 10 GX GPIO Performance
5.7.8. Guideline: Usage of I/O Bank 2A for External Memory Interfaces
6.1. Key Features of the Cyclone® 10 GX External Memory Interface Solution
6.2. Memory Standards Supported by Cyclone® 10 GX Devices
6.3. External Memory Interface Widths in Cyclone® 10 GX Devices
6.4. External Memory Interface I/O Pins in Cyclone® 10 GX Devices
6.5. Memory Interfaces Support in Cyclone® 10 GX Device Packages
6.6. External Memory Interface IP Support in Cyclone® 10 GX Devices
6.7. External Memory Interface Architecture of Cyclone® 10 GX Devices
6.8. External Memory Interfaces in Cyclone® 10 GX Devices Revision History
9.1. BST Operation Control
9.2. I/O Voltage for JTAG Operation
9.3. Performing BST
9.4. Enabling and Disabling IEEE Std. 1149.1 BST Circuitry
9.5. Guidelines for IEEE Std. 1149.1 Boundary-Scan Testing
9.6. IEEE Std. 1149.1 Boundary-Scan Register
9.7. IEEE Std. 1149.6 Boundary-Scan Register
9.8. JTAG Boundary-Scan Testing in Cyclone® 10 GX Devices Revision History
10.1. Power Consumption
10.2. Programmable Power Technology
10.3. Power Sense Line
10.4. Voltage Sensor
10.5. Temperature Sensing Diode
10.6. Power-On Reset Circuitry
10.7. Power Sequencing Considerations for Cyclone® 10 GX Devices
10.8. Power Supply Design
10.9. Power Management in Cyclone® 10 GX Devices Revision History
8.2.1.4. Evaluating Your System’s Response to Functional Upsets
The ratio of SEU strikes versus functional interrupts is the Single Event Functional Interrupt (SEFI) ratio. Minimizing this ratio improves SEU mitigation. SEUs can randomly strike any memory element, system testing is important to ensure a comprehensive recovery response.
You can use fault injection to aid in SEU recovery response. The fault injection feature allows you to operate the FPGA in your system and inject random CRAM bit flips to test the ability of the FPGA and the system to detect and recover fully from an SEU. You should be able to observe your FPGA and your system recover from these simulated SEU strikes. You can then refine your FPGA and system recovery sequence by observing these strikes. You can determine the SEFI rate of your design by using the fault injection feature.
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