Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

6.3. External Memory Interface Widths in Intel® Cyclone® 10 GX Devices

The Intel® Cyclone® 10 GX devices can support up to the following DDR3 external memory interfaces:

  • Two x40 interfaces with ECC
  • One x72 interface with ECC
Table 63.  Required I/O Banks for Interface Widths
  • This table lists the number of I/O banks required to support different external memory interface widths. You must implement each single memory interface using the I/O banks in the same I/O column.
  • This table is a guideline and represents the worst-case scenario for these interface widths. You can implement certain interfaces with fewer I/Os without using the whole I/O bank.
  • If the total number of address/command pins exceeds 36, you require one more I/O bank than the number listed in this table.
Interface Width Required Number of I/O Banks
x8 1
x16, x24, x32, x40 2
x48, x56, x64, x72 3

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