Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

7.3.6. Device Configuration Pins

Configuration Pins Summary

The following table lists the Intel® Cyclone® 10 GX configuration pins and their power supply.

Note: The TDI, TMS, TCK, TDO, and TRST pins are powered by VCCPGM .
Note: The CLKUSR, DEV_OE , DEV_CLRn , DATA[31..1] , and DATA0 pins are powered by VCCPGM during configuration and by VCCIO of the bank in which the pin resides if you use it as a user I/O pin.
Table 73.  Configuration Pin Summary for Intel® Cyclone® 10 GX Devices
Configuration Pin Configuration Scheme Input/Output User Mode Powered By
TDI JTAG Input VCCPGM
TMS JTAG Input VCCPGM
TCK JTAG Input VCCPGM
TDO JTAG Output VCCPGM
TRST JTAG Input VCCPGM
CLKUSR Optional, All schemes Input I/O VCCPGM /VCCIO 17
CRC_ERROR Optional, all schemes Output I/O VCCPGM /Pull-up
CONF_DONE All schemes Bidirectional VCCPGM /Pull-up
DCLK FPP and PS Input VCCPGM
AS Output VCCPGM
DEV_OE Optional, all schemes Input I/O VCCPGM /VCCIO 17
DEV_CLRn Optional, all schemes Input I/O VCCPGM /VCCIO 17
INIT_DONE Optional, all schemes Output I/O Pull-up
MSEL[2..0] All schemes Input VCCPGM
nSTATUS All schemes Bidirectional VCCPGM /Pull-up
nCE All schemes Input VCCPGM
nCEO Optional, All schemes Output I/O Pull-up
nCONFIG All schemes Input VCCPGM
DATA[31..1] FPP Input I/O VCCPGM /VCCIO 17
DATA0 FPP and PS Input I/O VCCPGM /VCCIO 17
nCSO[2..0] AS Output VCCPGM
nIO_PULLUP 18 All schemes Input VCC
AS_DATA[3..1] AS Bidirectional VCCPGM
AS_DATA0 / ASDO AS Bidirectional VCCPGM
17 This pin is powered by VCCPGM before and during configuration and is powered by VCCIO if used as a user I/O pin during user mode.
18 If you tie nIO_PULLUP pin to VCC, ensure that all user I/O pins and dual-purpose I/O pins are at logic 0 before and during configuration to prevent additional current to be drawn from the I/O pins.

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