Intel® Cyclone® 10 GX Core Fabric and General Purpose I/Os Handbook

ID 683775
Date 10/31/2022
Public
Document Table of Contents

4.1.5.3. RCLK Control Block

You can only control the clock source selection for the RCLK select block statically using configuration bit settings in the configuration file (.sof or .pof) generated by the Quartus® Prime Pro Edition software.

Figure 55. RCLK Control Block for Intel® Cyclone® 10 GX Devices


You can set the input clock sources and the clkena signals for the RCLK networks through the Quartus® Prime Pro Edition software using the ALTCLKCTRL IP core.

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