1. Partial Reconfiguration IP Core
You can perform partial reconfiguration through either an internal host residing in the core logic, or as an external host via dedicated device pins. The advantage of the internal host is that you store all the logic needed to perform PR on the device, without the need for external devices.
When you instantiate the PR IP core, the Main Controller module is instantiated. This module includes the Control Block (CB) Interface Controller, Freeze/Unfreeze Controller, Bitstream Decoder, and the Data Source Controller. A Data Source Interface module provides you with an optional JTAG Debug Interface and PR Data Interface. If you choose to use the PR IP core in internal host mode, the IP core automatically instantiates the corresponding crcblock and prblock WYSIWYG atom primitives.
If used as external host (placed in another FPGA or CPLD), the PR IP core provides the required interface ports. Connect to the dedicated PR pins and CRC_ERROR pin on the target FPGA undergoing partial reconfiguration.
The figure shows how to connect these blocks to the PR control block (CB). In your system, you include either the external host or the internal host, but not both. During PR, the PR Control Block (CB) is in Passive Parallel x16 programming mode for 28nm devices. In external host mode, the PR control block is not instantiated in the core of the device undergoing PR, because there is a direct connection from the external PR pins to the internal control block.
You can instantiate the PR IP core as the internal host for all supported devices. When you specify it as the internal host, both prblock and crcblock WYSIWYG atom primitives are auto-instantiated as part of the design. You can instantiate the PR IP core as the external host on any supported devices, as specified in the device family list.
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