Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

ID 683404
Date 4/18/2019

1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface

Partial Reconfiguration (PR) is available as a Platform Designer (Standard) or Platform Designer component through the Platform Designer (Standard) interface. Instantiate the core as an internal host or an external host.

You can configure the PR IP core to use Avalon-Streaming and Conduit interfaces, or an Avalon-MM interface. Enable the Avalon-MM interface using the Enable Avalon-MM Slave Interface option. If you use Qsys and want PR included as a component, for example in a design with both Platform Designer (Standard) and non-Platform Designer (Standard)partitions, you must instantiate the PR IP core in the Platform Designer (Standard) interface.

To instantiate the PR IP core with Qsys:
  1. Click Tools > Qsys.
  2. In the Qsys interface IP Catalog, click Basic Functions > Configuration and Programming and select Partial Reconfiguration.
  3. Configure your IP core variation using the settings appropriate to your design.
    Figure 3. Partial Reconfiguration IP Core in the Qsys Interface

  4. Optionally, turn on Enable Avalon-MM slave interface to use the Avalon Memory Map Slave interface rather than the Conduit interface.
  5. Turn on Enable enhanced decompression to use this optional feature.
  6. Select an appropriate clock-to-data ratio for your other options.
  7. Click Finish.