Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

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ID 683404
Date 4/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration IP Core
1. Partial Reconfiguration IP Core x
1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface 1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog 1.3. Enable Compression 1.4. Enable Enhanced Decompression 1.5. Data Compression Comparison 1.6. Bitstream Compatibility Check 1.7. Clock-to-Data Ratio (CD Ratio) 1.8. Partial Reconfiguration IP Core Parameters 1.9. Partial Reconfiguration IP Core Ports 1.10. Reconfiguration Sequence 1.11. Slave Interface 1.12. FPGA Control Block Interface 1.13. Freeze Logic for 28-nm PR Regions 1.14. Data Source Controller 1.15. Standard Partial Reconfiguration Data Interface 1.16. JTAG Debug Mode for Partial Reconfiguration 1.17. Partial Reconfiguration IP Core User Guide Archives 1.18. Revision History
1.3. Enable Compression x
1.3.1. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs) 1.3.2. Generating an Encrypted PR Bitstream
1.11. Slave Interface x
1.11.1. Interrupt Interface
1.12. FPGA Control Block Interface x
1.12.1. Partial Reconfiguration IP Core Timing Specification 1.12.2. Avalon® -MM Slave Interface Read and Write Transfer Timing
1.16. JTAG Debug Mode for Partial Reconfiguration x
1.16.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1. Partial Reconfiguration IP Core

1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface

Partial Reconfiguration (PR) is available as a Platform Designer (Standard) or Platform Designer component through the Platform Designer (Standard) interface. Instantiate the core as an internal host or an external host.

You can configure the PR IP core to use Avalon-Streaming and Conduit interfaces, or an Avalon-MM interface. Enable the Avalon-MM interface using the Enable Avalon-MM Slave Interface option. If you use Qsys and want PR included as a component, for example in a design with both Platform Designer (Standard) and non-Platform Designer (Standard)partitions, you must instantiate the PR IP core in the Platform Designer (Standard) interface.

To instantiate the PR IP core with Qsys:
  1. Click Tools > Qsys.
  2. In the Qsys interface IP Catalog, click Basic Functions > Configuration and Programming and select Partial Reconfiguration.
  3. Configure your IP core variation using the settings appropriate to your design.
    Figure 3. Partial Reconfiguration IP Core in the Qsys Interface


  4. Optionally, turn on Enable Avalon-MM slave interface to use the Avalon Memory Map Slave interface rather than the Conduit interface.
  5. Turn on Enable enhanced decompression to use this optional feature.
  6. Select an appropriate clock-to-data ratio for your other options.
  7. Click Finish.
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