Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

ID 683404
Date 4/18/2019

1.15. Standard Partial Reconfiguration Data Interface

The PR data interface provides you with selectable input data width; x1, x8, x16, and x32. The data interface is connected to ASMI_PARALLEL as well as the Avalon interface to obtain PR data from on-chip RAM, external flash device, or PR over PCIe.

For Cyclone® V and Stratix® V devices, if the input data width is other than x16, the PR IP core includes a data upsize or downsize module so that the data output to the Data Source Controller is always x16.