Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

ID 683404
Date 4/18/2019

1.11.1. Interrupt Interface

If you enable the Avalon® Memory Mapped Slave interface, you can use the optional interrupt interface of the Intel® Arria® 10 FPGA IP.

The IP core asserts irq during the following events:

Table 12.  Interrupt Interface Events
Status Code Event
3'b001 PR_ERROR occurred.
3'b010 CRC_ERROR occurred.
3'b011 The IP core detects an incompatible bitstream.
3'b101 The result of a successful PR operation.

After irq asserts, the master performs one or more of the following:

  • Query for the status of the PR IP core; PR_CSR[4:2].
  • Carry out some action, such as error reporting.
  • Once the interrupt is serviced, clear the interrupt by writing a "1" to PR_CSR[5].