Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

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ID 683404
Date 4/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration IP Core
1. Partial Reconfiguration IP Core x
1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface 1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog 1.3. Enable Compression 1.4. Enable Enhanced Decompression 1.5. Data Compression Comparison 1.6. Bitstream Compatibility Check 1.7. Clock-to-Data Ratio (CD Ratio) 1.8. Partial Reconfiguration IP Core Parameters 1.9. Partial Reconfiguration IP Core Ports 1.10. Reconfiguration Sequence 1.11. Slave Interface 1.12. FPGA Control Block Interface 1.13. Freeze Logic for 28-nm PR Regions 1.14. Data Source Controller 1.15. Standard Partial Reconfiguration Data Interface 1.16. JTAG Debug Mode for Partial Reconfiguration 1.17. Partial Reconfiguration IP Core User Guide Archives 1.18. Revision History
1.3. Enable Compression x
1.3.1. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs) 1.3.2. Generating an Encrypted PR Bitstream
1.11. Slave Interface x
1.11.1. Interrupt Interface
1.12. FPGA Control Block Interface x
1.12.1. Partial Reconfiguration IP Core Timing Specification 1.12.2. Avalon® -MM Slave Interface Read and Write Transfer Timing
1.16. JTAG Debug Mode for Partial Reconfiguration x
1.16.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1. Partial Reconfiguration IP Core

1.16. JTAG Debug Mode for Partial Reconfiguration

The JTAG debug mode allows you to configure partial reconfiguration bitstream through the JTAG interface. Use this feature to debug PR bitstream and eventually helping you in your PR design prototyping. This feature is available for internal and external host. Using the JTAG debug mode forces the Data Source Controller to be in x16 mode.

During JTAG debug operation, the JTAG command sent from the Intel® Quartus® Prime Programmer ignores and overrides most of the Partial Reconfiguration IP core interface signals (clk, pr_start, double_pr, data[], data_valid, and data_read).

Note: The TCK is the main clock source for PR IP core during this operation.

You can view the status of Partial Reconfiguration operation in the messages box and the Progress bar in the Intel® Quartus® Prime Programmer. The PR_DONE, PR_ERROR, and CRC_ERROR signals are monitored during PR operation and reported in the Messages box at the end of the operation.

The Intel® Quartus® Prime Programmer can detect the one or more PR_DONE instructions in plain or compressed PR bitstream and, therefore, can handle single or double PR cycle accordingly. However, only single PR cycle is supported for encrypted Partial Reconfiguration bitstream in JTAG debug mode (provided that the specified device is configured with the encrypted base bitstream which contains the PR IP core in the design).

Note: Configuring an incompatible PR bitstream to the specified device may corrupt your design, including the routing path and the PR IP core placed in the static region. When this issue occurs, the PR IP core stays in an undefined state, and the Intel® Quartus® Prime Programmer is unable to reset the IP core. As a result, the Intel® Quartus® Prime Programmer generates the following error when you try to configure a new PR bitstream: 
Error (12897): Partial Reconfiguration status: Can't reset the PR megafunction. This issue occurred because the design was corrupted by an incompatible PR bitstream in the previous PR operation. You must reconfigure the device with a good design.
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