1.11. Slave Interface
The Partial Reconfiguration Controller IP core provides an Avalon® -MM slave interface to read and write to PR configuration registers.
Every data write to this address indicates this bitstream is sent to the IP core.
Performing a read on this address returns all 0's.
|PR_CSR||0x01||Read or Write||Control and status registers.|
Read-only SW version register. Register is currently 0xAA500003
|PR Bitstream ID||0x03||Read-Only||Read-only PR POF ID register|
Read and write control register for pr_start signal. Refer to Input/Output Port List section for more details on the pr_start signal.
pr_start = PR_CSR
The IP core deasserts PR_CSR to value 0 automatically, one clock cycle after the PR_CSR asserts. This streamlines the flow to avoid manual assertion and de-assertion of this register to control pr_start signal.
Read and write control register for double_pr signal.
double_pr = PR_CSR
Read-only status register for status[2:0] signal.
PR_CSR[4:2] = status[2:0]
Read and clear bit for interrupt.
If you enable the interrupt interface, reading this bit returns the value of the irq signal. Writing a 1 clears the interrupt.
If you disable the interrupt interface, reading this bit always returns a value of 0.
|6-15||Reserved bits. Depends on the Avalon® -MM data bus width. When you use enhanced compression, data width limits to 16.|
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