1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface 1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog 1.3. Enable Compression 1.4. Enable Enhanced Decompression 1.5. Data Compression Comparison 1.6. Bitstream Compatibility Check 1.7. Clock-to-Data Ratio (CD Ratio) 1.8. Partial Reconfiguration IP Core Parameters 1.9. Partial Reconfiguration IP Core Ports 1.10. Reconfiguration Sequence 1.11. Slave Interface 1.12. FPGA Control Block Interface 1.13. Freeze Logic for 28-nm PR Regions 1.14. Data Source Controller 1.15. Standard Partial Reconfiguration Data Interface 1.16. JTAG Debug Mode for Partial Reconfiguration 1.17. Partial Reconfiguration IP Core User Guide Archives 1.18. Revision History
1.10. Reconfiguration Sequence
Partial reconfiguration occurs through the Avalon® -MM slave interface in the following sequence:
- Avalon® -MM master component writes 0x01 (or 0x03 if the design requires double PR) to IP address offset 0x1 to trigger PR operation.
- Avalon® -MM master component writes PR bitstream to IP address offset 0x0, until all the PR bitstream writes. When enhanced decompression is on, waitrequest activates throughout the PR operation. Ensure that your master can handle waitrequest from the slave interface.
- Avalon® -MM master component reads the data from IP address offset 0x1 to check the status[2:0] value. Optionally, the Avalon® -MM master component reads the status[2:0] of this IP during a PR operation to detect any early failure, for example, PR_ERROR.
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