Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

ID 683404
Date 4/18/2019

1.10. Reconfiguration Sequence

Partial reconfiguration occurs through the Avalon® -MM slave interface in the following sequence:
  1. Avalon® -MM master component writes 0x01 (or 0x03 if the design requires double PR) to IP address offset 0x1 to trigger PR operation.
  2. Avalon® -MM master component writes PR bitstream to IP address offset 0x0, until all the PR bitstream writes. When enhanced decompression is on, waitrequest activates throughout the PR operation. Ensure that your master can handle waitrequest from the slave interface.
  3. Avalon® -MM master component reads the data from IP address offset 0x1 to check the status[2:0] value. Optionally, the Avalon® -MM master component reads the status[2:0] of this IP during a PR operation to detect any early failure, for example, PR_ERROR.

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