Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

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ID 683404
Date 4/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration IP Core
1. Partial Reconfiguration IP Core x
1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface 1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog 1.3. Enable Compression 1.4. Enable Enhanced Decompression 1.5. Data Compression Comparison 1.6. Bitstream Compatibility Check 1.7. Clock-to-Data Ratio (CD Ratio) 1.8. Partial Reconfiguration IP Core Parameters 1.9. Partial Reconfiguration IP Core Ports 1.10. Reconfiguration Sequence 1.11. Slave Interface 1.12. FPGA Control Block Interface 1.13. Freeze Logic for 28-nm PR Regions 1.14. Data Source Controller 1.15. Standard Partial Reconfiguration Data Interface 1.16. JTAG Debug Mode for Partial Reconfiguration 1.17. Partial Reconfiguration IP Core User Guide Archives 1.18. Revision History
1.3. Enable Compression x
1.3.1. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs) 1.3.2. Generating an Encrypted PR Bitstream
1.11. Slave Interface x
1.11.1. Interrupt Interface
1.12. FPGA Control Block Interface x
1.12.1. Partial Reconfiguration IP Core Timing Specification 1.12.2. Avalon® -MM Slave Interface Read and Write Transfer Timing
1.16. JTAG Debug Mode for Partial Reconfiguration x
1.16.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1. Partial Reconfiguration IP Core

1.12.1. Partial Reconfiguration IP Core Timing Specification

The following timing diagram illustrates a successful Partial Reconfiguration IP core operation. You determine whether the operations passes or fails with the status[2:0] output signal.

The PR operation is initiated when you assert the pr_start signal. Monitor the status[] or freeze signals to detect the end of the PR operation.

Figure 7. Partial Reconfiguration Timing


Note:
  • You must assert pr_start signal high for a minimum of one clock cycle to initiate PR, Deassert pr_start before sending the last data.
  • status[] signal is reset when pr_start is asserted. This signal changes during a PR operation if any error such as a CRC_ERROR, PR_ERROR, or bitstream incompatibility error is detected.
  • status[] signal changes after a PR operation if CRC_ERROR is detected and no error happens during the previous PR operation.
  • The data_valid signal is not required to be asserted at the same time as the pr_start. You can provide the data[] and assert data_valid when appropriate.
  • You can either drive the data_valid signal low after sending the last data, or continue to assert data_valid high with dummy data on data[] until the end of PR, when freeze is driven low or status[] is updated.
  • data[] is transferred only when data_valid and data_ready are asserted on the same cycle. Do not drive new data on the data bus, when both data_valid and data_ready are not high.
  • The data_ready signal is driven low once the PR IP core receives the last data.

The data[], data_valid, and data_ready signals comply with the Avalon-ST specification for Data Transfer with Backpressure. The PR IP Core acts as a sink, with readLatency set to 0. For more information, refer to the Avalon Interface Specifications.

Important: The PR_CLK signal has a different nominal maximum frequency for each device. Most Stratix® V devices have a nominal maximum frequency of at least 62.5 MHz.
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