Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

ID 683404
Date 4/18/2019

1.12.1. Partial Reconfiguration IP Core Timing Specification

The following timing diagram illustrates a successful Partial Reconfiguration IP core operation. You determine whether the operations passes or fails with the status[2:0] output signal.

The PR operation is initiated when you assert the pr_start signal. Monitor the status[] or freeze signals to detect the end of the PR operation.

Figure 7. Partial Reconfiguration Timing

  • You must assert pr_start signal high for a minimum of one clock cycle to initiate PR, Deassert pr_start before sending the last data.
  • status[] signal is reset when pr_start is asserted. This signal changes during a PR operation if any error such as a CRC_ERROR, PR_ERROR, or bitstream incompatibility error is detected.
  • status[] signal changes after a PR operation if CRC_ERROR is detected and no error happens during the previous PR operation.
  • The data_valid signal is not required to be asserted at the same time as the pr_start. You can provide the data[] and assert data_valid when appropriate.
  • You can either drive the data_valid signal low after sending the last data, or continue to assert data_valid high with dummy data on data[] until the end of PR, when freeze is driven low or status[] is updated.
  • data[] is transferred only when data_valid and data_ready are asserted on the same cycle. Do not drive new data on the data bus, when both data_valid and data_ready are not high.
  • The data_ready signal is driven low once the PR IP core receives the last data.

The data[], data_valid, and data_ready signals comply with the Avalon-ST specification for Data Transfer with Backpressure. The PR IP Core acts as a sink, with readLatency set to 0. For more information, refer to the Avalon Interface Specifications.

Important: The PR_CLK signal has a different nominal maximum frequency for each device. Most Stratix® V devices have a nominal maximum frequency of at least 62.5 MHz.

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