Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

ID 683404
Date 4/18/2019
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1.16.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode

To configure the Partial Reconfiguration bitstream in JTAG debug mode, follow these steps:
  1. In the Intel® Quartus® Prime Programmer GUI, right click a highlighted base bitstream (in .sof) and then click Add PR Programming File to add the PR bitstream (.rbf).
    Figure 10. Adding PR Programming File
  2. After adding the PR bitstream, you can change or delete the Partial Reconfiguration programming file by clicking Change PR Programming File or Delete PR Programming File.
    Figure 11. Change PR Programming File or Delete PR Programming File
  3. Click Start to configure the PR bitstream. The Intel® Quartus® Prime Programmer generates an error message if the specified device does not contain the PR IP core in the design (you must instantiate the Partial Reconfiguration IP core in your design to use the JTAG debug mode).
    Figure 12. Starting PR Bitstream Configuration
  4. Configure the valid .rbf in JTAG debug mode with the Intel® Quartus® Prime Programmer.
    Figure 13. Configuring Valid .rbf
  5. The JTAG debug mode is also supported if the PR IP core is pre-programmed on the specified device.
    Figure 14. Partial Reconfiguration IP Core Successfully Pre-programmed
  6. The Intel® Quartus® Prime Programmer reports error when you try to configure the corrupted .rbf in JTAG debug mode.
    Figure 15. Configuring Corrupted .rbf