Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

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ID 683404
Date 4/18/2019
Public
Document Table of Contents
Document Table of Contents x
1. Partial Reconfiguration IP Core
1. Partial Reconfiguration IP Core x
1.1. Instantiating the Partial Reconfiguration IP Core in the Qsys Interface 1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog 1.3. Enable Compression 1.4. Enable Enhanced Decompression 1.5. Data Compression Comparison 1.6. Bitstream Compatibility Check 1.7. Clock-to-Data Ratio (CD Ratio) 1.8. Partial Reconfiguration IP Core Parameters 1.9. Partial Reconfiguration IP Core Ports 1.10. Reconfiguration Sequence 1.11. Slave Interface 1.12. FPGA Control Block Interface 1.13. Freeze Logic for 28-nm PR Regions 1.14. Data Source Controller 1.15. Standard Partial Reconfiguration Data Interface 1.16. JTAG Debug Mode for Partial Reconfiguration 1.17. Partial Reconfiguration IP Core User Guide Archives 1.18. Revision History
1.3. Enable Compression x
1.3.1. PR Bitstream Compression and Encryption ( Intel® Arria® 10 Designs) 1.3.2. Generating an Encrypted PR Bitstream
1.11. Slave Interface x
1.11.1. Interrupt Interface
1.12. FPGA Control Block Interface x
1.12.1. Partial Reconfiguration IP Core Timing Specification 1.12.2. Avalon® -MM Slave Interface Read and Write Transfer Timing
1.16. JTAG Debug Mode for Partial Reconfiguration x
1.16.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode
1. Partial Reconfiguration IP Core

1.16.1. Configuring Partial Reconfiguration Bitstream in JTAG Debug Mode

To configure the Partial Reconfiguration bitstream in JTAG debug mode, follow these steps:
  1. In the Intel® Quartus® Prime Programmer GUI, right click a highlighted base bitstream (in .sof) and then click Add PR Programming File to add the PR bitstream (.rbf).
    Figure 10. Adding PR Programming File
  2. After adding the PR bitstream, you can change or delete the Partial Reconfiguration programming file by clicking Change PR Programming File or Delete PR Programming File.
    Figure 11. Change PR Programming File or Delete PR Programming File
  3. Click Start to configure the PR bitstream. The Intel® Quartus® Prime Programmer generates an error message if the specified device does not contain the PR IP core in the design (you must instantiate the Partial Reconfiguration IP core in your design to use the JTAG debug mode).
    Figure 12. Starting PR Bitstream Configuration
  4. Configure the valid .rbf in JTAG debug mode with the Intel® Quartus® Prime Programmer.
    Figure 13. Configuring Valid .rbf
  5. The JTAG debug mode is also supported if the PR IP core is pre-programmed on the specified device.
    Figure 14. Partial Reconfiguration IP Core Successfully Pre-programmed
  6. The Intel® Quartus® Prime Programmer reports error when you try to configure the corrupted .rbf in JTAG debug mode.
    Figure 15. Configuring Corrupted .rbf
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