Intel® Quartus® Prime Standard Edition User Guide: Partial Reconfiguration Intel® FPGA IP

ID 683404
Date 4/18/2019

1.2. Instantiating the Partial Reconfiguration IP Core in the Intel® Quartus® Prime IP Catalog

Partial Reconfiguration (PR) is available from the IP Catalog. You can choose to instantiate the core as an internal host or an external host.
If you are not using PR as a component of the Qsys interface, then you can instantiate PR with the Intel® Quartus® Prime IP Catalog.
  1. Click Tools > IP Catalog.
  2. Click Installed IP > Library > Basic Functions > Configuration and Programming and select Partial Reconfiguration.
  3. In the Save IP Variation dialog box, type the name for your partial reconfiguration IP variation. Choose whether to use Verilog or VHDL. Click OK to save your variation.
  4. Configure your IP core variation using the settings appropriate to your design.
    Figure 4. Partial Reconfiguration IP Core in the IP Catalog

  5. Optionally, turn on Enable Avalon-MM slave interface to use the Avalon Memory Map Slave interface rather than the Conduit interface.
  6. Turn on Enable enhanced decompression to use this optional feature.
  7. Select an appropriate clock-to-data ratio for your other options.
  8. Click Finish.
    The IP Catalog instantiates your IP core variation and displays a completion dialog box.

  9. Click Exit.