AN 798: Partial Reconfiguration with the Arria 10 HPS

ID 683034
Date 1/25/2017
Document Table of Contents

Partial Reconfiguration with the Intel® Arria® 10 HPS

Partial reconfiguration (PR) allows you to reconfigure a portion of the FPGA dynamically, while the remaining FPGA design continues to function.

With partial reconfiguration, you can create multiple logic implementations for specific physical regions of the device, and reload any desired implementation at runtime. This methodology is effective in systems where multiple functions time-share the same FPGA device resources. PR enables the implementation of more complex FPGA systems.

Because Arria 10 SoC devices include the hard processor system (HPS), you can use software running on the device itself to load and reload multiple logic images. The HPS can retrieve images from a remote location, for example via Ethernet, allowing system updates and remote logic image management.