AN 798: Partial Reconfiguration with the Arria 10 HPS

ID 683034
Date 1/25/2017
Public
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Critical Information in the Default Device Tree

Listed below is the critical information provided in the default device tree, which is located with the Linux kernel source. /soc/base_fpga_region defines an empty FPGA region that is filled in by loading a device tree overlay after boot. This entry links to the FPGA manager, which is used to configure this FPGA region. In the example in this document, you add a PR FPGA region as a child node of /soc/base_fpga_region . This region inherits the link to the FPGA manager created in this boot device tree.

socfpga-linux/arch/arm/boot/dts/socfpga_arria10.dtsi

/ {
	#address-cells = <1>;
	#size-cells = <1>;
        
        soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		device_type = "soc";
		interrupt-parent = <&intc>;
		ranges;

		base_fpga_region {
			compatible = "fpga-region";
			fpga-mgr = <&fpga_mgr>;

			#address-cells = <0x1>;
			#size-cells = <0x1>;
			
			/*
			 * NOTE: This node will be the parent for
			 *       the PR FPGA Region that is managed
			 *       using device tree overlays. The child
			 *       FPGA Regions will inherit the link to
			 *       the FPGA Manger created here.
			 */
		};

		fpga_mgr: fpga-mgr@ffd03000 {
			compatible = "altr,socfpga-a10-fpga-mgr";
			reg = <0xffd03000 0x100
			       0xffcfe400 0x20>;
			clocks = <&l4_mp_clk>;
			resets = <&rst FPGAMGR_RESET>;
			reset-names = "fpgamgr";
		};

        };                
};