Advantages of Partial Reconfiguration Scope of This Document Prerequisites for Using This Document Partial Reconfiguration Tools and Methods Arria 10 SoC Partial Reconfiguration Workflow Partial Reconfiguration Limitations Creating the PR Example Design Generating the Example Software Image Loading Partial Reconfiguration Designs Using Linux Important Partial Reconfiguration Terminology Revision History
Qsys Partial Reconfiguration Freeze Logic Importing the GHRD Project Add a Partial Reconfiguration Region to the GHRD Building the Base Revision with the Reconfigurable Design Partition Synthesizing an Alternate Persona Implementing the Alternate Persona Generating the RBF FPGA Image Files Design Handoff to Software Developer
To create software for an SoC partial reconfiguration design, you create a device tree overlay that describes the static portion of your design (the base revision). Then, you create device tree overlays for personas in each PR region.
In this application note, you create and run a PR software example based on the GHRD. You start with a base device tree for the SoC, distributed with your kernel. Then you carry out steps to adapt this device tree to the PR example design.