AN 798: Partial Reconfiguration with the Arria 10 HPS

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ID 683034
Date 1/25/2017
Public
Document Table of Contents
Document Table of Contents x
Partial Reconfiguration with the Intel® Arria® 10 HPS
Partial Reconfiguration with the Intel® Arria® 10 HPS x
Advantages of Partial Reconfiguration Scope of This Document Prerequisites for Using This Document Partial Reconfiguration Tools and Methods Arria 10 SoC Partial Reconfiguration Workflow Partial Reconfiguration Limitations Creating the PR Example Design Generating the Example Software Image Loading Partial Reconfiguration Designs Using Linux Important Partial Reconfiguration Terminology Revision History
Prerequisites for Using This Document x
Knowledge Prerequisites Software Tool Prerequisites Hardware Prerequisites
Partial Reconfiguration Tools and Methods x
Hardware Tools and Methods Software Tools and Methods
Hardware Tools and Methods x
Arria 10 SoC Partial Reconfiguration Support Overview of the Arria 10 GHRD
Arria 10 SoC Partial Reconfiguration Workflow x
Hardware Workflow Software Workflow
Creating the PR Example Design x
Qsys Partial Reconfiguration Freeze Logic Importing the GHRD Project Add a Partial Reconfiguration Region to the GHRD Building the Base Revision with the Reconfigurable Design Partition Synthesizing an Alternate Persona Implementing the Alternate Persona Generating the RBF FPGA Image Files Design Handoff to Software Developer
Qsys Partial Reconfiguration Freeze Logic x
PR Freeze Bridge PR Freeze Controller
Add a Partial Reconfiguration Region to the GHRD x
Creating the Partial Reconfiguration Design Adding the PR Region Connecting New Ports in the GHRD Module Instantiation
Generating the Example Software Image x
Overview of Software Image Creation Generating a New Boot Device Tree Creating the Device Tree Overlays
Generating a New Boot Device Tree x
Critical Information in the Default Device Tree Steps to Create a New Device Tree
Loading Partial Reconfiguration Designs Using Linux x
Installing Files on the SD Card Loading and Unloading the Device Tree Overlays
Partial Reconfiguration with the Intel® Arria® 10 HPS

Hardware Prerequisites

This example is based on the 16.1 release of the SoC Golden System Reference Design (GSRD). For information about the GSRD, go to the Getting Started page of rocketboards.org, and look for documentation for the 16.1 SoC development kit.

An SoC Development Kit is required. It must be configured to boot from the SD card for this example. The SD card must be updated to the 16.1 version of the GSRD.

To create an SD card, follow the instructions in the Arria 10 GSRD v16.1 Getting Started Guide on rocketboards.org. Alternatively, you can use the follwoing shortcut to create an SD card in a Linux development environment:

  1. Download the GSRD 16.1 binary tar file from rocketboards.org.
  2. Extract the sdcard image as follows:
    tar xvfz linux-socfpga-gsrd-16.1-a10-bin.tar.gz sdimage.tar.gz
tar xvfz sdimage.tar.gz
  3. Copy the SD card image to the SD card as follows:
    sudo dd if=sdimage.img of=/dev/{sd card device}
    Note: The SD card must be at least 2 GB in size.
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