AN 798: Partial Reconfiguration with the Arria 10 HPS

ID 683034
Date 1/25/2017
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Arria 10 SoC Partial Reconfiguration Workflow

Fully implementing PR for the SoC FPGA, using the Arm* processor-based Hard Processor System (HPS) to manage reconfigurable regions, requires coordination between the FPGA logic designer and the HPS host software developer. Certain information must be provided by the FPGA logic designer to the host software developer in order for PR management to work correctly and reliably with the HPS.