AN 798: Partial Reconfiguration with the Arria 10 HPS

ID 683034
Date 1/25/2017
Public
Document Table of Contents
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Creating the Device Tree Overlays

Three device tree overlay files are needed for this example. The first overlay updates the system description to add the new node containing the reconfigurable region. The other two overlays are used to describe the two PR region personas.

  1. Create a new file named base_static.dtso with the following contents. Note that the freeze Ccontroller type and base address must be entered into the appropriate fields.
    
    /dts-v1//plugin/;
    
    / {
    
      fragment@0 {
        target-path = "/soc/base_fpga_region";
        #address-cells = <0x1>;
        #size-cells = <0x1>;
        
        __overlay__ {
          ranges = <0x0 0x0 0xc0000000 0x40000 0x1 0x0 0xff200000 0x1000>;
          external-fpga-config;
          #address-cells = <0x2>;
          #size-cells = <0x1>;
          
          fpga_pr_region0 {
            compatible = "fpga-region";
            fpga-bridges = <&freeze_controller_0>;
            ranges;
          };
          
          freeze_controller_0: freeze_controller@0x100000450 {
            compatible = "altr,freeze_controller-16.1", \
              "altr,freeze-bridge-controller";
            reg = <0x1 0x450 0x10>;
          };
        };
      };
    };
    
  2. Create a file named pr_region_default.dtso with the following contents. Note that the system ID peripheral base address is required.
    
    /dts-v1//plugin/;
    
    / {
    
      fragment@1 {
        target-path = "/soc/base_fpga_region/fpga_pr_region0";
        #address-cells = <0x1>;
        #size-cells = <0x1>;
    
        __overlay__ {
          partial-fpga-config;
          firmware-name = "pr_region_default.rbf";
          #address-cells = <0x2>;
          #size-cells = <0x1>;
          region-unfreeze-timeout-us = <0x4>;
          region-freeze-timeout-us = <0x4>;
    
          sysid@0x100000800 {
            compatible = "altr,sysid-16.1", "altr,sysid-1.0";
            reg = <0x1 0x800 0x8>;
          };
        };
      };
    };
                      
                   
  3. Create a file named pr_region_alt.dtso with the following contents. Note that the system ID peripheral base address is different from the default persona.
    
    /dts-v1//plugin/;
    
    / {
    
      fragment@1 {
        target-path = "/soc/base_fpga_region/fpga_pr_region0";
        #address-cells = <0x1>;
        #size-cells = <0x1>;
    
        __overlay__ {
          partial-fpga-config;
          firmware-name = "pr_region_alt.rbf";
          #address-cells = <0x2>;
          #size-cells = <0x1>;
          region-unfreeze-timeout-us = <0x4>;
          region-freeze-timeout-us = <0x4>;
    
          sysid@0x100000A00 {
            compatible = "altr,sysid-16.1", "altr,sysid-1.0";
            reg = <0x1 0xA00 0x8>;
          };
        };
      };
    };
    
  4. Load the embedded_command_shell.sh environment provided by the SoC EDS tools. This environment provides the device tree compiler command dtc. Use dtc to compile the newly created Device Tree Source (DTS) files to Device Tree Blob (DTB) files as shown below.
    
    $ dtc -@ -I dts -O dtb -o base_static.dtbo base_static.dtso
    $ dtc -@ -I dts -O dtb -o pr_region_default.dtbo pr_region_default.dtso
    $ dtc -@ -I dts -O dtb -o pr_region_alt.dtbo pr_region_alt.dtso