AN 798: Partial Reconfiguration with the Arria 10 HPS

ID 683034
Date 1/25/2017
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Advantages of Partial Reconfiguration

PR provides the following advantages over designs without PR:

  • Allows runtime design reconfiguration
  • Improves design scalability by time-sharing hardware resources
  • Lowers cost and power consumption through efficient use of board space
  • Improves initial programming time through smaller bitstreams
  • Reduces system down-time by enabling live updates
  • Facilitates system update by allowing fast, low-risk remote hardware changes

PR is a way to load different or updated soft logic without disturbing the HPS host software. Performing a full FPGA image configuration in an Intel® SoC FPGA resets and reconfigures all shared I/O and DDR memory interfaces. Therefore, full reconfiguration can crash the HPS host software if it is using the shared I/O or DDR memory at the time. In contrast, loading a reconfigurable logic region does not affect these critical interfaces.