AN 798: Partial Reconfiguration with the Arria 10 HPS

ID 683034
Date 1/25/2017
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Hardware Tools and Methods

The PR design flow requires you to use the project revisions feature in the Quartus Prime Pro software. Your initial design is the base revision. In this revision, you define the physical boundaries in the device of the static region, which does not change under partial reconfiguration, and the reconfigurable regions, which do change.

From the base revision, you create multiple revisions. These revisions contain the different implementations for the PR regions.

Figure 1. Regions and Personas

The implementation of an FPGA design with PR results in multiple FPGA configuration image files. One file is loaded initially, and the others are subsequently loaded to reconfigure FPGA logic. The first image loaded is an FPGA configuration containing the base static region and the default implementation, or persona, for each reconfigurable region. One additional configuration image is generated for each persona of each reconfiguration region. Loading one of these additional files causes the reconfiguration of the associated region to the alternate persona.

The management of reconfigurable logic regions is performed most efficiently using the FPGA Manager peripheral module within the HPS block, independent of the type of host software.

PR requires logical isolation of reconfigurable FPGA regions while they are being modified. This is called freeze logic.