AN 798: Partial Reconfiguration with the Arria 10 HPS

ID 683034
Date 1/25/2017
Document Table of Contents

Partial Reconfiguration Limitations

Reconfigurable partitions can contain only core resources, such as LABs, embedded memory blocks (M20Ks and MLABs), and DSP blocks in the FPGA. All periphery resources, such as transceivers, external memory interfaces, GPIOs, I/O receivers, and hard processor system (HPS), must be in the static portion of the design. Partial reconfiguration of global network buffers for clocks and resets is not possible.