Advantages of Partial Reconfiguration Scope of This Document Prerequisites for Using This Document Partial Reconfiguration Tools and Methods Arria 10 SoC Partial Reconfiguration Workflow Partial Reconfiguration Limitations Creating the PR Example Design Generating the Example Software Image Loading Partial Reconfiguration Designs Using Linux Important Partial Reconfiguration Terminology Revision History
Qsys Partial Reconfiguration Freeze Logic Importing the GHRD Project Add a Partial Reconfiguration Region to the GHRD Building the Base Revision with the Reconfigurable Design Partition Synthesizing an Alternate Persona Implementing the Alternate Persona Generating the RBF FPGA Image Files Design Handoff to Software Developer
The PR hardware design flow requires initial planning. This planning involves:
- Planning design partition(s), logical divisions in the source code hierarchy. Well-planned PR partitions improve design area utilization and performance.
- Determining the placement assignments in the floorplan (the physical design layout on the device).
After you have planned the partitions and floorplan, you are ready to set up the design hierarchy and source code to support this partitioning.